Nasm Instruction Set Reference

This is derived from the old, obsolete, and potentially buggy instruction set reference from the old Nasm Manual. The Nasm development team explicitly disclaims any responsibility for errors and omissions in this document!

This manual documents NASM, the Netwide Assembler: an assembler targetting the Intel x86 series of processors, with portable source.

Index

Appendix A: x86 Instruction Reference
Section A.1: Key to Operand Specifications
Section A.2: Key to Opcode Descriptions
Section A.2.1: Register Values
Section A.2.2: Condition Codes
Section A.2.3: SSE Condition Predicates
Section A.2.4: Status Flags
Section A.2.5: Effective Address Encoding: ModR/M and SIB
Section A.2.6: Register Extensions: The REX Prefix
Section A.3: Key to Instruction Flags
Section A.4: x86 Instruction Set
Section A.4.1: AAA, AAS, AAM, AAD: ASCII Adjustments
Section A.4.2: ADC: Add with Carry
Section A.4.3: ADD: Add Integers
Section A.4.4: ADDPD: ADD Packed Double-Precision FP Values
Section A.4.5: ADDPS: ADD Packed Single-Precision FP Values
Section A.4.6: ADDSD: ADD Scalar Double-Precision FP Values
Section A.4.7: ADDSS: ADD Scalar Single-Precision FP Values
Section A.4.8: AND: Bitwise AND
Section A.4.9: ANDNPD: Bitwise Logical AND NOT of Packed Double-Precision FP Values
Section A.4.10: ANDNPS: Bitwise Logical AND NOT of Packed Single-Precision FP Values
Section A.4.11: ANDPD: Bitwise Logical AND For Single FP
Section A.4.12: ANDPS: Bitwise Logical AND For Single FP
Section A.4.13: ARPL: Adjust RPL Field of Selector
Section A.4.14: BOUND: Check Array Index against Bounds
Section A.4.15: BSF, BSR: Bit Scan
Section A.4.16: BSWAP: Byte Swap
Section A.4.17: BT, BTC, BTR, BTS: Bit Test
Section A.4.18: CALL: Call Subroutine
Section A.4.19: CBW, CWD, CDQ, CWDE: Sign Extensions
Section A.4.20: CLC, CLD, CLI, CLTS: Clear Flags
Section A.4.21: CLFLUSH: Flush Cache Line
Section A.4.22: CMC: Complement Carry Flag
Section A.4.23: CMOVcc: Conditional Move
Section A.4.24: CMP: Compare Integers
Section A.4.25: CMPccPD: Packed Double-Precision FP Compare
Section A.4.26: CMPccPS: Packed Single-Precision FP Compare
Section A.4.27: CMPSB, CMPSW, CMPSD: Compare Strings
Section A.4.28: CMPccSD: Scalar Double-Precision FP Compare
Section A.4.29: CMPccSS: Scalar Single-Precision FP Compare
Section A.4.30: CMPXCHG, CMPXCHG486: Compare and Exchange
Section A.4.31: CMPXCHG8B: Compare and Exchange Eight Bytes
Section A.4.32: COMISD: Scalar Ordered Double-Precision FP Compare and Set EFLAGS
Section A.4.33: COMISS: Scalar Ordered Single-Precision FP Compare and Set EFLAGS
Section A.4.34: CPUID: Get CPU Identification Code
Section A.4.35: CVTDQ2PD: Packed Signed INT32 to Packed Double-Precision FP Conversion
Section A.4.36: CVTDQ2PS: Packed Signed INT32 to Packed Single-Precision FP Conversion
Section A.4.37: CVTPD2DQ: Packed Double-Precision FP to Packed Signed INT32 Conversion
Section A.4.38: CVTPD2PI: Packed Double-Precision FP to Packed Signed INT32 Conversion
Section A.4.39: CVTPD2PS: Packed Double-Precision FP to Packed Single-Precision FP Conversion
Section A.4.40: CVTPI2PD: Packed Signed INT32 to Packed Double-Precision FP Conversion
Section A.4.41: CVTPI2PS: Packed Signed INT32 to Packed Single-FP Conversion
Section A.4.42: CVTPS2DQ: Packed Single-Precision FP to Packed Signed INT32 Conversion
Section A.4.43: CVTPS2PD: Packed Single-Precision FP to Packed Double-Precision FP Conversion
Section A.4.44: CVTPS2PI: Packed Single-Precision FP to Packed Signed INT32 Conversion
Section A.4.45: CVTSD2SI: Scalar Double-Precision FP to Signed INT32 Conversion
Section A.4.46: CVTSD2SS: Scalar Double-Precision FP to Scalar Single-Precision FP Conversion
Section A.4.47: CVTSI2SD: Signed INT32 to Scalar Double-Precision FP Conversion
Section A.4.48: CVTSI2SS: Signed INT32 to Scalar Single-Precision FP Conversion
Section A.4.49: CVTSS2SD: Scalar Single-Precision FP to Scalar Double-Precision FP Conversion
Section A.4.50: CVTSS2SI: Scalar Single-Precision FP to Signed INT32 Conversion
Section A.4.51: CVTTPD2DQ: Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation
Section A.4.52: CVTTPD2PI: Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation
Section A.4.53: CVTTPS2DQ: Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation
Section A.4.54: CVTTPS2PI: Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation
Section A.4.55: CVTTSD2SI: Scalar Double-Precision FP to Signed INT32 Conversion with Truncation
Section A.4.56: CVTTSS2SI: Scalar Single-Precision FP to Signed INT32 Conversion with Truncation
Section A.4.57: DAA, DAS: Decimal Adjustments
Section A.4.58: DEC: Decrement Integer
Section A.4.59: DIV: Unsigned Integer Divide
Section A.4.60: DIVPD: Packed Double-Precision FP Divide
Section A.4.61: DIVPS: Packed Single-Precision FP Divide
Section A.4.62: DIVSD: Scalar Double-Precision FP Divide
Section A.4.63: DIVSS: Scalar Single-Precision FP Divide
Section A.4.64: EMMS: Empty MMX State
Section A.4.65: ENTER: Create Stack Frame
Section A.4.66: F2XM1: Calculate 2**X-1
Section A.4.67: FABS: Floating-Point Absolute Value
Section A.4.68: FADD, FADDP: Floating-Point Addition
Section A.4.69: FBLD, FBSTP: BCD Floating-Point Load and Store
Section A.4.70: FCHS: Floating-Point Change Sign
Section A.4.71: FCLEX, FNCLEX: Clear Floating-Point Exceptions
Section A.4.72: FCMOVcc: Floating-Point Conditional Move
Section A.4.73: FCOM, FCOMP, FCOMPP, FCOMI, FCOMIP: Floating-Point Compare
Section A.4.74: FCOS: Cosine
Section A.4.75: FDECSTP: Decrement Floating-Point Stack Pointer
Section A.4.76: FxDISI, FxENI: Disable and Enable Floating-Point Interrupts
Section A.4.77: FDIV, FDIVP, FDIVR, FDIVRP: Floating-Point Division
Section A.4.78: FEMMS: Faster Enter/Exit of the MMX or floating-point state
Section A.4.79: FFREE: Flag Floating-Point Register as Unused
Section A.4.80: FIADD: Floating-Point/Integer Addition
Section A.4.81: FICOM, FICOMP: Floating-Point/Integer Compare
Section A.4.82: FIDIV, FIDIVR: Floating-Point/Integer Division
Section A.4.83: FILD, FIST, FISTP: Floating-Point/Integer Conversion
Section A.4.84: FIMUL: Floating-Point/Integer Multiplication
Section A.4.85: FINCSTP: Increment Floating-Point Stack Pointer
Section A.4.86: FINIT, FNINIT: initialize Floating-Point Unit
Section A.4.87: FISUB: Floating-Point/Integer Subtraction
Section A.4.88: FLD: Floating-Point Load
Section A.4.89: FLDxx: Floating-Point Load Constants
Section A.4.90: FLDCW: Load Floating-Point Control Word
Section A.4.91: FLDENV: Load Floating-Point Environment
Section A.4.92: FMUL, FMULP: Floating-Point Multiply
Section A.4.93: FNOP: Floating-Point No Operation
Section A.4.94: FPATAN, FPTAN: Arctangent and Tangent
Section A.4.95: FPREM, FPREM1: Floating-Point Partial Remainder
Section A.4.96: FRNDINT: Floating-Point Round to Integer
Section A.4.97: FSAVE, FRSTOR: Save/Restore Floating-Point State
Section A.4.98: FSCALE: Scale Floating-Point Value by Power of Two
Section A.4.99: FSETPM: Set Protected Mode
Section A.4.100: FSIN, FSINCOS: Sine and Cosine
Section A.4.101: FSQRT: Floating-Point Square Root
Section A.4.102: FST, FSTP: Floating-Point Store
Section A.4.103: FSTCW: Store Floating-Point Control Word
Section A.4.104: FSTENV: Store Floating-Point Environment
Section A.4.105: FSTSW: Store Floating-Point Status Word
Section A.4.106: FSUB, FSUBP, FSUBR, FSUBRP: Floating-Point Subtract
Section A.4.107: FTST: Test ST0 Against Zero
Section A.4.108: FUCOMxx: Floating-Point Unordered Compare
Section A.4.109: FXAM: Examine Class of Value in ST0
Section A.4.110: FXCH: Floating-Point Exchange
Section A.4.111: FXRSTOR: Restore FP, MMX and SSE State
Section A.4.112: FXSAVE: Store FP, MMX and SSE State
Section A.4.113: FXTRACT: Extract Exponent and Significand
Section A.4.114: FYL2X, FYL2XP1: Compute Y times Log2(X) or Log2(X+1)
Section A.4.115: HLT: Halt Processor
Section A.4.116: IBTS: Insert Bit String
Section A.4.117: IDIV: Signed Integer Divide
Section A.4.118: IMUL: Signed Integer Multiply
Section A.4.119: IN: Input from I/O Port
Section A.4.120: INC: Increment Integer
Section A.4.121: INSB, INSW, INSD: Input String from I/O Port
Section A.4.122: INT: Software Interrupt
Section A.4.123: INT3, INT1, ICEBP, INT01: Breakpoints
Section A.4.124: INTO: Interrupt if Overflow
Section A.4.125: INVD: Invalidate Internal Caches
Section A.4.126: INVLPG: Invalidate TLB Entry
Section A.4.127: IRET, IRETW, IRETD: Return from Interrupt
Section A.4.128: Jcc: Conditional Branch
Section A.4.129: JCXZ, JECXZ: Jump if CX/ECX Zero
Section A.4.130: JMP: Jump
Section A.4.131: LAHF: Load AH from Flags
Section A.4.132: LAR: Load Access Rights
Section A.4.133: LDMXCSR: Load Streaming SIMD Extension Control/Status
Section A.4.134: LDS, LES, LFS, LGS, LSS: Load Far Pointer
Section A.4.135: LEA: Load Effective Address
Section A.4.136: LEAVE: Destroy Stack Frame
Section A.4.137: LFENCE: Load Fence
Section A.4.138: LGDT, LIDT, LLDT: Load Descriptor Tables
Section A.4.139: LMSW: Load/Store Machine Status Word
Section A.4.140: LOADALL, LOADALL286: Load Processor State
Section A.4.141: LODSB, LODSW, LODSD: Load from String
Section A.4.142: LOOP, LOOPE, LOOPZ, LOOPNE, LOOPNZ: Loop with Counter
Section A.4.143: LSL: Load Segment Limit
Section A.4.144: LTR: Load Task Register
Section A.4.145: MASKMOVDQU: Byte Mask Write
Section A.4.146: MASKMOVQ: Byte Mask Write
Section A.4.147: MAXPD: Return Packed Double-Precision FP Maximum
Section A.4.148: MAXPS: Return Packed Single-Precision FP Maximum
Section A.4.149: MAXSD: Return Scalar Double-Precision FP Maximum
Section A.4.150: MAXSS: Return Scalar Single-Precision FP Maximum
Section A.4.151: MFENCE: Memory Fence
Section A.4.152: MINPD: Return Packed Double-Precision FP Minimum
Section A.4.153: MINPS: Return Packed Single-Precision FP Minimum
Section A.4.154: MINSD: Return Scalar Double-Precision FP Minimum
Section A.4.155: MINSS: Return Scalar Single-Precision FP Minimum
Section A.4.156: MOV: Move Data
Section A.4.157: MOVAPD: Move Aligned Packed Double-Precision FP Values
Section A.4.158: MOVAPS: Move Aligned Packed Single-Precision FP Values
Section A.4.159: MOVD: Move Doubleword to/from MMX Register
Section A.4.160: MOVDQ2Q: Move Quadword from XMM to MMX register.
Section A.4.161: MOVDQA: Move Aligned Double Quadword
Section A.4.162: MOVDQU: Move Unaligned Double Quadword
Section A.4.163: MOVHLPS: Move Packed Single-Precision FP High to Low
Section A.4.164: MOVHPD: Move High Packed Double-Precision FP
Section A.4.165: MOVHPS: Move High Packed Single-Precision FP
Section A.4.166: MOVLHPS: Move Packed Single-Precision FP Low to High
Section A.4.167: MOVLPD: Move Low Packed Double-Precision FP
Section A.4.168: MOVLPS: Move Low Packed Single-Precision FP
Section A.4.169: MOVMSKPD: Extract Packed Double-Precision FP Sign Mask
Section A.4.170: MOVMSKPS: Extract Packed Single-Precision FP Sign Mask
Section A.4.171: MOVNTDQ: Move Double Quadword Non Temporal
Section A.4.172: MOVNTI: Move Doubleword Non Temporal
Section A.4.173: MOVNTPD: Move Aligned Four Packed Single-Precision FP Values Non Temporal
Section A.4.174: MOVNTPS: Move Aligned Four Packed Single-Precision FP Values Non Temporal
Section A.4.175: MOVNTQ: Move Quadword Non Temporal
Section A.4.176: MOVQ: Move Quadword to/from MMX Register
Section A.4.177: MOVQ2DQ: Move Quadword from MMX to XMM register.
Section A.4.178: MOVSB, MOVSW, MOVSD: Move String
Section A.4.179: MOVSD: Move Scalar Double-Precision FP Value
Section A.4.180: MOVSS: Move Scalar Single-Precision FP Value
Section A.4.181: MOVSX, MOVZX: Move Data with Sign or Zero Extend
Section A.4.182: MOVUPD: Move Unaligned Packed Double-Precision FP Values
Section A.4.183: MOVUPS: Move Unaligned Packed Single-Precision FP Values
Section A.4.184: MUL: Unsigned Integer Multiply
Section A.4.185: MULPD: Packed Single-FP Multiply
Section A.4.186: MULPS: Packed Single-FP Multiply
Section A.4.187: MULSD: Scalar Single-FP Multiply
Section A.4.188: MULSS: Scalar Single-FP Multiply
Section A.4.189: NEG, NOT: Two's and One's Complement
Section A.4.190: NOP: No Operation
Section A.4.191: OR: Bitwise OR
Section A.4.192: ORPD: Bit-wise Logical OR of Double-Precision FP Data
Section A.4.193: ORPS: Bit-wise Logical OR of Single-Precision FP Data
Section A.4.194: OUT: Output Data to I/O Port
Section A.4.195: OUTSB, OUTSW, OUTSD: Output String to I/O Port
Section A.4.196: PACKSSDW, PACKSSWB, PACKUSWB: Pack Data
Section A.4.197: PADDB, PADDW, PADDD: Add Packed Integers
Section A.4.198: PADDQ: Add Packed Quadword Integers
Section A.4.199: PADDSB, PADDSW: Add Packed Signed Integers With Saturation
Section A.4.200: PADDSIW: MMX Packed Addition to Implicit Destination
Section A.4.201: PADDUSB, PADDUSW: Add Packed Unsigned Integers With Saturation
Section A.4.202: PAND, PANDN: MMX Bitwise AND and AND-NOT
Section A.4.203: PAUSE: Spin Loop Hint
Section A.4.204: PAVEB: MMX Packed Average
Section A.4.205: PAVGB PAVGW: Average Packed Integers
Section A.4.206: PAVGUSB: Average of unsigned packed 8-bit values
Section A.4.207: PCMPxx: Compare Packed Integers.
Section A.4.208: PDISTIB: MMX Packed Distance and Accumulate with Implied Register
Section A.4.209: PEXTRW: Extract Word
Section A.4.210: PF2ID: Packed Single-Precision FP to Integer Convert
Section A.4.211: PF2IW: Packed Single-Precision FP to Integer Word Convert
Section A.4.212: PFACC: Packed Single-Precision FP Accumulate
Section A.4.213: PFADD: Packed Single-Precision FP Addition
Section A.4.214: PFCMPxx: Packed Single-Precision FP Compare
Section A.4.215: PFMAX: Packed Single-Precision FP Maximum
Section A.4.216: PFMIN: Packed Single-Precision FP Minimum
Section A.4.217: PFMUL: Packed Single-Precision FP Multiply
Section A.4.218: PFNACC: Packed Single-Precision FP Negative Accumulate
Section A.4.219: PFPNACC: Packed Single-Precision FP Mixed Accumulate
Section A.4.220: PFRCP: Packed Single-Precision FP Reciprocal Approximation
Section A.4.221: PFRCPIT1: Packed Single-Precision FP Reciprocal, First Iteration Step
Section A.4.222: PFRCPIT2: Packed Single-Precision FP Reciprocal/ Reciprocal Square Root, Second Iteration Step
Section A.4.223: PFRSQIT1: Packed Single-Precision FP Reciprocal Square Root, First Iteration Step
Section A.4.224: PFRSQRT: Packed Single-Precision FP Reciprocal Square Root Approximation
Section A.4.225: PFSUB: Packed Single-Precision FP Subtract
Section A.4.226: PFSUBR: Packed Single-Precision FP Reverse Subtract
Section A.4.227: PI2FD: Packed Doubleword Integer to Single-Precision FP Convert
Section A.4.228: PF2IW: Packed Word Integer to Single-Precision FP Convert
Section A.4.229: PINSRW: Insert Word
Section A.4.230: PMACHRIW: Packed Multiply and Accumulate with Rounding
Section A.4.231: PMADDWD: MMX Packed Multiply and Add
Section A.4.232: PMAGW: MMX Packed Magnitude
Section A.4.233: PMAXSW: Packed Signed Integer Word Maximum
Section A.4.234: PMAXUB: Packed Unsigned Integer Byte Maximum
Section A.4.235: PMINSW: Packed Signed Integer Word Minimum
Section A.4.236: PMINUB: Packed Unsigned Integer Byte Minimum
Section A.4.237: PMOVMSKB: Move Byte Mask To Integer
Section A.4.238: PMULHRWC, PMULHRIW: Multiply Packed 16-bit Integers With Rounding, and Store High Word
Section A.4.239: PMULHRWA: Multiply Packed 16-bit Integers With Rounding, and Store High Word
Section A.4.240: PMULHUW: Multiply Packed 16-bit Integers, and Store High Word
Section A.4.241: PMULHW, PMULLW: Multiply Packed 16-bit Integers, and Store
Section A.4.242: PMULUDQ: Multiply Packed Unsigned 32-bit Integers, and Store.
Section A.4.243: PMVccZB: MMX Packed Conditional Move
Section A.4.244: POP: Pop Data from Stack
Section A.4.245: POPAx: Pop All General-Purpose Registers
Section A.4.246: POPFx: Pop Flags Register
Section A.4.247: POR: MMX Bitwise OR
Section A.4.248: PREFETCH: Prefetch Data Into Caches
Section A.4.249: PREFETCHh: Prefetch Data Into Caches
Section A.4.250: PSADBW: Packed Sum of Absolute Differences
Section A.4.251: PSHUFD: Shuffle Packed Doublewords
Section A.4.252: PSHUFHW: Shuffle Packed High Words
Section A.4.253: PSHUFLW: Shuffle Packed Low Words
Section A.4.254: PSHUFW: Shuffle Packed Words
Section A.4.255: PSLLx: Packed Data Bit Shift Left Logical
Section A.4.256: PSRAx: Packed Data Bit Shift Right Arithmetic
Section A.4.257: PSRLx: Packed Data Bit Shift Right Logical
Section A.4.258: PSUBx: Subtract Packed Integers
Section A.4.259: PSUBSxx, PSUBUSx: Subtract Packed Integers With Saturation
Section A.4.260: PSUBSIW: MMX Packed Subtract with Saturation to Implied Destination
Section A.4.261: PSWAPD: Swap Packed Data
Section A.4.262: PUNPCKxxx: Unpack and Interleave Data
Section A.4.263: PUSH: Push Data on Stack
Section A.4.264: PUSHAx: Push All General-Purpose Registers
Section A.4.265: PUSHFx: Push Flags Register
Section A.4.266: PXOR: MMX Bitwise XOR
Section A.4.267: RCL, RCR: Bitwise Rotate through Carry Bit
Section A.4.268: RCPPS: Packed Single-Precision FP Reciprocal
Section A.4.269: RCPSS: Scalar Single-Precision FP Reciprocal
Section A.4.270: RDMSR: Read Model-Specific Registers
Section A.4.271: RDPMC: Read Performance-Monitoring Counters
Section A.4.272: RDSHR: Read SMM Header Pointer Register
Section A.4.273: RDTSC: Read Time-Stamp Counter
Section A.4.274: RET, RETF, RETN: Return from Procedure Call
Section A.4.275: ROL, ROR: Bitwise Rotate
Section A.4.276: RSDC: Restore Segment Register and Descriptor
Section A.4.277: RSLDT: Restore Segment Register and Descriptor
Section A.4.278: RSM: Resume from System-Management Mode
Section A.4.279: RSQRTPS: Packed Single-Precision FP Square Root Reciprocal
Section A.4.280: RSQRTSS: Scalar Single-Precision FP Square Root Reciprocal
Section A.4.281: RSTS: Restore TSR and Descriptor
Section A.4.282: SAHF: Store AH to Flags
Section A.4.283: SAL, SAR: Bitwise Arithmetic Shifts
Section A.4.284: SALC: Set AL from Carry Flag
Section A.4.285: SBB: Subtract with Borrow
Section A.4.286: SCASB, SCASW, SCASD: Scan String
Section A.4.287: SETcc: Set Register from Condition
Section A.4.288: SFENCE: Store Fence
Section A.4.289: SGDT, SIDT, SLDT: Store Descriptor Table Pointers
Section A.4.290: SHL, SHR: Bitwise Logical Shifts
Section A.4.291: SHLD, SHRD: Bitwise Double-Precision Shifts
Section A.4.292: SHUFPD: Shuffle Packed Double-Precision FP Values
Section A.4.293: SHUFPS: Shuffle Packed Single-Precision FP Values
Section A.4.294: SMI: System Management Interrupt
Section A.4.295: SMINT, SMINTOLD: Software SMM Entry (CYRIX)
Section A.4.296: SMSW: Store Machine Status Word
Section A.4.297: SQRTPD: Packed Double-Precision FP Square Root
Section A.4.298: SQRTPS: Packed Single-Precision FP Square Root
Section A.4.299: SQRTSD: Scalar Double-Precision FP Square Root
Section A.4.300: SQRTSS: Scalar Single-Precision FP Square Root
Section A.4.301: STC, STD, STI: Set Flags
Section A.4.302: STMXCSR: Store Streaming SIMD Extension Control/Status
Section A.4.303: STOSB, STOSW, STOSD: Store Byte to String
Section A.4.304: STR: Store Task Register
Section A.4.305: SUB: Subtract Integers
Section A.4.306: SUBPD: Packed Double-Precision FP Subtract
Section A.4.307: SUBPS: Packed Single-Precision FP Subtract
Section A.4.308: SUBSD: Scalar Single-FP Subtract
Section A.4.309: SUBSS: Scalar Single-FP Subtract
Section A.4.310: SVDC: Save Segment Register and Descriptor
Section A.4.311: SVLDT: Save LDTR and Descriptor
Section A.4.312: SVTS: Save TSR and Descriptor
Section A.4.313: SYSCALL: Call Operating System
Section A.4.314: SYSENTER: Fast System Call
Section A.4.315: SYSEXIT: Fast Return From System Call
Section A.4.316: SYSRET: Return From Operating System
Section A.4.317: TEST: Test Bits (notional bitwise AND)
Section A.4.318: UCOMISD: Unordered Scalar Double-Precision FP compare and set EFLAGS
Section A.4.319: UCOMISS: Unordered Scalar Single-Precision FP compare and set EFLAGS
Section A.4.320: UD0, UD1, UD2: Undefined Instruction
Section A.4.321: UMOV: User Move Data
Section A.4.322: UNPCKHPD: Unpack and Interleave High Packed Double-Precision FP Values
Section A.4.323: UNPCKHPS: Unpack and Interleave High Packed Single-Precision FP Values
Section A.4.324: UNPCKLPD: Unpack and Interleave Low Packed Double-Precision FP Data
Section A.4.325: UNPCKLPS: Unpack and Interleave Low Packed Single-Precision FP Data
Section A.4.326: VERR, VERW: Verify Segment Readability/Writability
Section A.4.327: WAIT: Wait for Floating-Point Processor
Section A.4.328: WBINVD: Write Back and Invalidate Cache
Section A.4.329: WRMSR: Write Model-Specific Registers
Section A.4.330: WRSHR: Write SMM Header Pointer Register
Section A.4.331: XADD: Exchange and Add
Section A.4.332: XBTS: Extract Bit String
Section A.4.333: XCHG: Exchange
Section A.4.334: XLATB: Translate Byte in Lookup Table
Section A.4.335: XOR: Bitwise Exclusive OR
Section A.4.336: XORPD: Bitwise Logical XOR of Double-Precision FP Values
Section A.4.337: XORPS: Bitwise Logical XOR of Single-Precision FP Values